The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2019
Filed:
Dec. 21, 2012
Applicant:
Hewlett-packard Development Company, L.p., Houston, TX (US);
Inventors:
Gregory Trezise, Gifford Bristol, GB;
Andrew Hana, Gifford Bristol, GB;
Assignee:
Hewlett Packard Enterprise Development LP, Houston, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 5/04 (2006.01); G06F 3/06 (2006.01); G11C 29/02 (2006.01); G11C 29/42 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1076 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 3/0683 (2013.01); G06F 11/1052 (2013.01); G11C 5/04 (2013.01); G11C 29/028 (2013.01); G11C 29/42 (2013.01); G11C 29/52 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01);
Abstract
A memory module includes an error correction logic to provide data error protection for data stored in the memory module. The error correction logic is selectively controllable between an enabled state and a disabled state. Data stored in the memory module is without error protection provided by the memory module if the error correction logic is in the disabled state.