The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2019
Filed:
Sep. 02, 2016
Applicant:
Giga-byte Technology Co.,ltd., New Taipei, TW;
Inventors:
Assignee:
GIGA-BYTE TECHNOLOGY CO., LTD., New Taipei, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/14 (2006.01); G06F 9/4401 (2018.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4401 (2013.01); G06F 13/4022 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01);
Abstract
A BIOS control method for PCI-E lanes includes the following steps. A BIOS obtains information of whether a first expansion card and a second expansion card are respectively inserted in a first PCI-E slot and a second PCI-E slot, and if the second expansion card is inserted in the second PCI-E slot, then the BIOS instructs a CPU to reverse the order of PCI-E lanes electrically connected between the CPU and the second PCI-E slot.
Sun, Pei-Hua. (2019). Bios control method for pci-e lane (U.S. Patent No. 10203961). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10203961
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile