The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Aug. 27, 2014
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Junichi Segawa, Kawasaki, JP;

Tatsunori Kanai, Yokohama, JP;

Tetsuro Kimura, Tokyo, JP;

Koichi Fujisaki, Kawasaki, JP;

Masaya Tarui, Yokohama, JP;

Satoshi Shirai, Kawasaki, JP;

Hiroyoshi Haruki, Kawasaki, JP;

Yusuke Shirota, Yokohama, JP;

Akihiro Shibata, Tokyo, JP;

Shiyo Yoshimura, Kawasaki, JP;

Haruhiko Toyama, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3215 (2013.01); G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 1/3237 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1221 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1285 (2013.01); Y02D 10/126 (2018.01); Y02D 10/128 (2018.01); Y02D 10/14 (2018.01); Y02D 10/172 (2018.01);
Abstract

According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited. When the processor enters the second state and if an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state in which power consumption is lower as compared to the first state. If the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state in which power consumption is lower as compared to the third state.


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