The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Feb. 16, 2017
Applicant:

Innolux Corporation, Miao-Li County, TW;

Inventors:

Te-Yi Chen, Miao-Li County, TW;

Han-Tsung Su, Miao-Li County, TW;

Hsin-Hung Lin, Miao-Li County, TW;

Ker-Yih Kao, Miao-Li County, TW;

Assignee:

Innolux Corporation, Miao-Li County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 29/66 (2006.01); G02F 1/1335 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); G02F 1/133512 (2013.01); G02F 1/133514 (2013.01); G02F 2001/134345 (2013.01); G02F 2001/136236 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/122 (2013.01); G02F 2201/123 (2013.01); H01L 29/786 (2013.01);
Abstract

An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.


Find Patent Forward Citations

Loading…