The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2019

Filed:

Jun. 01, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Franco Motika, Hopewell Junction, NY (US);

John D. Parker, Fishkill, NY (US);

Gerard M. Salem, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/317 (2006.01); G01R 31/28 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318307 (2013.01); G01R 31/2834 (2013.01); G01R 31/3177 (2013.01); G01R 31/31704 (2013.01); G01R 31/31724 (2013.01); G01R 31/318371 (2013.01);
Abstract

Embodiments include methods, computer systems and computer program products for generating functional test patterns for diagnostics, characterization and manufacture test. Aspects include: receiving from a system designer, via a design verification tool module, certain verification sequences configured to verify system functional design, executing the verification sequences received at a functional exerciser module against a device to generate various traces, capturing traces generated in emulation compatible format, processing traces captured via trace processor module, including parsing the traces captured, verifying data integrity of the traces captured, and summarizing statistics of the traces captured, generating, via an emulated pattern generator module, a predetermined number of emulated test patterns having tester independent format 'streams' of data compatible with a device test port based on output of the trace processor module, and processing, via a tester specific post-processor module, the emulated test patterns to generate functional test patterns using a tester specific post-processor module.


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