The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

May. 22, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Ju-pyung Lee, Incheon, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/173 (2006.01); H04L 29/08 (2006.01); G06F 9/50 (2006.01); G06F 21/80 (2013.01); H04L 29/06 (2006.01); H04L 12/923 (2013.01);
U.S. Cl.
CPC ...
H04L 67/1012 (2013.01); G06F 9/505 (2013.01); G06F 21/80 (2013.01); H04L 47/762 (2013.01); H04L 63/0245 (2013.01); H04L 63/10 (2013.01); H04L 67/101 (2013.01); H04L 67/1002 (2013.01); H04L 67/1008 (2013.01);
Abstract

An operating method of a memory system including a storage array including a plurality of segments and a first server node and a second server node allocating and managing the plurality of segments includes: requesting, via the first server node, load information from the second server node before performing a memory operation; receiving, via the first server node, the load information from the second server node and comparing load information of the first server node with the load information of the second server node; performing, via the first server node, a load balancing operation, based on a comparison result; and performing, via the first server node, a segment dynamic allocation operation regarding the storage array, the segment dynamic allocation operation matching the load balancing operation.


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Lee, Ju-pyung. (2019). Memory system including plurality of server nodes sharing storage array and operating method of memory system (U.S. Patent No. 10200462). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10200462

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