Memory controller, semiconductor memory system and operating method thereof

Abstract

An operation method of a memory controller includes: reading a second data from memory cells when a hard decision error correction decoding operation based on a first data read from the memory cells fails; calculating a LLR of each bit-data included in the first data by using the first and second data; and performing a soft decision error correction decoding operation based on the LLR, wherein the memory cells include a first and second memory cell, wherein the first data includes first-bit-data read from the first and second memory cell, wherein the second data includes second-bit-data read from the first and second memory cell, wherein the LLR is a LLR of the first-bit-data read from the first memory cell calculated based on the first bit and a second bit read from the first memory cell and a first bit and a second bit read from the second memory cell.