The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Sep. 12, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Osamu Matsuura, Kuwana, JP;

Hideki Inokuma, Yokkaichi, JP;

Masanari Fujita, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 29/7843 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar structure, at least one charge storage film, and a first electrode. The stacked body includes electrode films stacked separately from each other. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in stacking direction of the stacked body. The charge storage film is provided between the semiconductor layer and the electrode films. The first electrode is provided in the stacked body, spreads in the stacking direction and a first direction along a surface of the substrate, and contacting the substrate. The first electrode includes a first portion containing a material having conductivity and a second portion containing a material that a linear expansion coefficient is lower than a linear expansion coefficient of silicon, and positioned at a substrate side than the first portion in the stacking direction.


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