Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.