The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Jul. 09, 2014
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Yasuhiro Araki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H04N 5/374 (2011.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14643 (2013.01); H01L 27/14605 (2013.01); H01L 27/14612 (2013.01); H01L 27/14623 (2013.01); H01L 27/14636 (2013.01); H01L 27/14641 (2013.01); H01L 27/14689 (2013.01); H04N 5/374 (2013.01); H04N 5/37457 (2013.01);
Abstract

A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions. The first transistor is arranged within the pixel region, between one floating capacitance region and the other floating capacitance region of the two floating capacitance regions with respect to a direction in which the one floating capacitance region and the other floating capacitance region are aligned.


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