The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Nov. 22, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Donghyun Kim, Suwon-si, KR;

DooWon Kwon, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01); F01P 7/04 (2006.01); F01P 11/20 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/02 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 27/1464 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); F01P 7/048 (2013.01); F01P 11/20 (2013.01); F01P 2050/24 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/17106 (2013.01); H01L 2224/32012 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73203 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.


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