The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2019
Filed:
Dec. 31, 2016
Applicant:
Sandisk Technologies Llc, Plano, TX (US);
Inventors:
Assignee:
SANDISK TECHNOLOGIES LLC, Plano, TX (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/362 (2006.01); G06F 13/42 (2006.01); G06F 12/02 (2006.01); G11C 7/22 (2006.01); G11C 29/02 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 13/3625 (2013.01); G06F 12/0238 (2013.01); G06F 13/4291 (2013.01); G11C 7/222 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G06F 2212/202 (2013.01); G11C 7/1039 (2013.01);
Abstract
A device includes a first latch configured to be coupled to a bus and configured to receive a data signal and a clock signal. The device also includes a delay element configured to generate a delayed version of the data signal or a delayed version of the clock signal. A second latch is coupled to the delay element and configured to receive the delayed version of the data signal or the delayed version of the clock signal. The device further includes a comparator coupled to the first latch and the second latch. The comparator is configured to receive a first output from the first latch and a second output from the second latch.