The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2019
Filed:
Apr. 15, 2015
Applicant:
Sanechips Technology Co., Ltd., Shenzhen, Guangdong, CN;
Inventor:
Jianping Jiang, Shenzhen, CN;
Assignee:
Sanechips Technology Co. Ltd., Shenzhen, Guangdong, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/16 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1678 (2013.01); G06F 13/364 (2013.01); G06F 13/38 (2013.01); G06F 13/4018 (2013.01); G06F 13/4022 (2013.01); G06F 13/4265 (2013.01); G06F 13/4282 (2013.01);
Abstract
A method for implementing a configurable on-chip interconnection system. The method comprises: in an interconnection system, master devices set bit widths of bus identifiers of the master devices, wherein the bit widths of the bus identifiers of the master devices are the same (); and in a memory access process, the mater devices interact, by means of interconnection matrices only, with slave devices according to the bus identifiers (). Also provided are a system and apparatus for implementing the method, and a storage medium.