The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Apr. 11, 2016
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Shuai Che, Bellevue, WA (US);

Marc S. Orr, Bellevue, WA (US);

Bradford M. Beckmann, Bellevue, WA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 12/10 (2016.01); G06F 12/0802 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0837 (2016.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30087 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0837 (2013.01); G06F 12/0802 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/10 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/452 (2013.01);
Abstract

A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.


Find Patent Forward Citations

Loading…