The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Jun. 01, 2016
Applicant:

Advanced Micro Device, Inc., Sunnyvale, CA (US);

Inventors:

Kevin M. Brandl, Austin, TX (US);

Thomas H. Hamilton, Manor, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 5/14 (2006.01); G11C 11/34 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0629 (2013.01); G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0673 (2013.01); G11C 5/14 (2013.01); G11C 11/34 (2013.01); G11C 11/4074 (2013.01); G11C 11/40615 (2013.01); G11C 2029/0411 (2013.01); G11C 2207/2227 (2013.01);
Abstract

In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded fields. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the entry. In another form, a system comprises a memory system and a processor coupled to the memory system. The processor is adapted to access the memory module using such a memory controller.


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