The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Feb. 16, 2017
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Do-Sun Hong, Icheon-si Gyeonggi-do, KR;

Donggun Kim, Icheon-si Gyeonggi-do, KR;

Yong Ju Kim, Icheon-si Gyeonggi-do, KR;

Sang Gu Jo, Icheon-si Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/29 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 12/02 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/073 (2013.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); G06F 12/0246 (2013.01); G11C 13/004 (2013.01); G11C 13/0033 (2013.01); G11C 13/0069 (2013.01); G06F 2212/202 (2013.01); G06F 2212/657 (2013.01);
Abstract

A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.


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