The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2019
Filed:
Dec. 18, 2017
Palo Alto Research Center Incorporated, Palo Alto, CA (US);
Robert A. Street, Palo Alto, CA (US);
Julie A. Bert, East Palo Alto, CA (US);
John C. Knights, Soquel, CA (US);
PALO ALTO RESEARCH CENTER INCORPORATED, Palo Alto, CA (US);
Abstract
A flexible TFT backplane includes, a flexible substrate, a first set of address line contacts associated with the substrate, and a second set of address line contacts associated with the substrate. The first set of address line contacts and the second set of address line contacts are located at opposite sides of the substrate from each other, defining a vertical direction. A first set of address lines designed to run in one of the vertical direction and a diagonal or non-vertical direction with respect to the defined vertical direction, with the first set of address lines connected to the first set of address line contacts. Also provided is a second set of address lines designed to run in one of a diagonal or non-vertical direction with respect to the defined vertical direction, and a combination of diagonal and horizontal directions with respect to the vertical direction, with the second set of address lines connected to the second set of address line contacts. At least one insulating layer is located between the first set of address lines and the second set of address lines, and a plurality of TFTs arranged in an array, within the boundaries of the substrate, wherein the TFTs are addressed by the first set of address lines and the second set of address lines.