The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Mar. 25, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bruce J. Chamberlin, Vestal, NY (US);

Joseph Kuczynski, Rochester, MN (US);

Paula M. Nixa, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/00 (2006.01); H05K 3/46 (2006.01); H05K 3/30 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4611 (2013.01); H05K 2201/09136 (2013.01); H05K 2203/068 (2013.01);
Abstract

A printed circuit board and method of manufacturing same, the printed circuit board comprising a stack of layers. The stack of layers being comprised of alternating circuit layers and insulating layers that are laminated together. The stack of layers includes an area with resin cured to a degree. The area has a coefficient of thermal expansion that is dependent, at least in part, on the degree of curing of the resin.


Find Patent Forward Citations

Chamberlin, Bruce. (2019). Minimizing printed circuit board warpage (U.S. Patent No. 10194537). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10194537

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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