Hot carrier injection tolerant network on chip router architecture

Abstract

For a hot carrier injection tolerant network on chip (NoC) router architecture, a plurality of input buffers receives a plurality of input data bits. A plurality of multiplexers shuffles the plurality of input data bits to output a plurality of shuffled input buffer data bits. A coupling module switches first input buffer data bits at the plurality of input buffers from first shuffled input buffer data bits to second shuffled input buffer data bits using the plurality of multiplexers. A selector selects, using a plurality of decoders, a virtual channel path to a virtual channel of the plurality of virtual channels for the shuffled input buffer data bits. A connection module switches the second shuffled input buffer data bits from a first virtual channel to a second virtual channel of the plurality of virtual channels using the plurality of decoders.