The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Feb. 16, 2017
Applicant:

Avago Technologies International Sales Pte. Limited, Singapore, SG;

Inventors:

Hiroshi Kimura, San Jose, CA (US);

Haoqiong Chen, San Jose, CA (US);

Yehui Sun, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 (2006.01); H04L 25/03 (2006.01); H03K 19/0175 (2006.01); H03K 17/16 (2006.01); H04L 27/01 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03025 (2013.01); H04L 25/03343 (2013.01); H03K 17/161 (2013.01); H03K 19/017509 (2013.01); H04L 27/01 (2013.01);
Abstract

To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.


Find Patent Forward Citations

Kimura, Hiroshi. (2019). Continuous time pre-cursor and post-cursor compensation circuits (U.S. Patent No. 10193714). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10193714

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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