The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Sep. 05, 2014
Applicant:
Phison Electronics Corp., Miaoli, TW;
Inventors:
Assignee:
PHISON ELECTRONICS CORP., Miaoli, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H04L 1/00 (2006.01); H03M 13/25 (2006.01); G06F 11/07 (2006.01); H03M 13/37 (2006.01); H03M 13/29 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1128 (2013.01); G06F 11/076 (2013.01); H03M 13/255 (2013.01); H03M 13/2948 (2013.01); H03M 13/3707 (2013.01); H03M 13/3746 (2013.01); H03M 13/3753 (2013.01); H04L 1/005 (2013.01);
Abstract
A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.