The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Aug. 28, 2017
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Erik Pankratz, Austin, TX (US);

Arnab Dutta, Austin, TX (US);

Assignee:

SILICON LABORATORIES INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03K 17/22 (2006.01); H03K 19/0185 (2006.01); H03K 5/24 (2006.01);
U.S. Cl.
CPC ...
H03K 17/223 (2013.01); H03K 5/2472 (2013.01); H03K 19/018521 (2013.01);
Abstract

A POR circuit for a secondary supply domain of an IC. A bias and reference circuit provides startup current and a reference voltage for a comparator. The comparator compares the reference voltage with a primary supply voltage and develops a bias current. The bias and reference circuit and the comparator includes a VGS loop which mirrors the bias current to develop the reference voltage. When the comparator switches, the bias current is at the low quiescent current level. A level shift and isolation circuit initially isolates a primary POR signal from the secondary domain. When the comparator switches, the primary POR signal is detected and level shifted to control the reset state. The delay circuit senses ramping of the secondary supply voltage and provides a delayed secondary POR signal a predetermined time period after the secondary supply voltage achieves a predetermined voltage threshold to additionally control the reset state.


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