The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Jan. 05, 2018
Applicant:

Werlatone, Inc., Brewster, NY (US);

Inventors:

Carl G. Schuster, New Milford, CT (US);

Bernard J. Werlau, Brewster, NY (US);

Peter A. Kuring, Sherman, CT (US);

Ky-Hien Do, Mississauga, CA;

Assignee:

Werlatone, Inc., Brewster, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/07 (2006.01); H03F 3/60 (2006.01); H03F 3/213 (2006.01); H03K 5/02 (2006.01); H03F 3/195 (2006.01); H04B 1/04 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03F 3/602 (2013.01); H03F 3/195 (2013.01); H03F 3/213 (2013.01); H03K 5/02 (2013.01); H03F 2200/336 (2013.01); H03F 2200/451 (2013.01); H03K 2005/00286 (2013.01); H04B 1/0475 (2013.01);
Abstract

In some embodiments, a power divider/combiner assembly includes a divider network, a plurality of amplifiers, and a combiner network. The divider network divides a received divider-network input signal into N divider-network output signals. The divider network includes at least one divider and at least one divider phase-shift circuit. The plurality of amplifiers include N amplifiers for amplifying the divider-network signals. The combiner network is for combining the N amplified signals into a combiner-network output signal. The combiner network includes at least one combiner and at least one combiner phase-shift circuit. Each phase-shift circuit is configured to produce a respective non-zero phase shift between divider output signals or between combiner input signals.


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