The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

May. 05, 2017
Applicant:

Synaptics Incorporated, San Jose, CA (US);

Inventor:

Abhijat Goyal, Lakeway, TX (US);

Assignee:

SYNAPTICS INCORPORATED, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/045 (2006.01); H02H 9/04 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); G06F 3/044 (2013.01); H02H 9/044 (2013.01); G06F 2203/04108 (2013.01);
Abstract

Embodiments of disclosure generally relate to integrated circuits (ICs) and, more particularly, a voltage-triggered edge-insensitive electrostatic discharge (ESD) clamp for protection of ICs. An example trigger circuit is provided for controlling a current shunt in an IC. The trigger circuit generally includes a comparison circuit configured to compare a monitored voltage to a reference voltage and output a signal indicating when the monitored voltage reaches or exceeds the reference voltage; and a shunt circuit configured to shunt the current based on receiving the signal from the comparison circuit. The voltage-triggered edge-insensitive clamp provides a single protection circuit that protects against all types of ESD and/or electrostatic overstress (EOS) events.


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Goyal, Abhijat. (2019). Voltage triggered edge insensitive protection circuit (U.S. Patent No. 10193338). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10193338

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