The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Sep. 14, 2017
Applicants:
Boe Technology Group Co., Ltd., Beijing, CN;
Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;
Inventors:
Yanwei Ren, Beijing, CN;
Chaochao Sun, Beijing, CN;
Kunpeng Zhang, Beijing, CN;
Yezhou Fang, Beijing, CN;
Jingyi Xu, Beijing, CN;
Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); G03F 7/30 (2006.01); H01L 27/32 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); G03F 7/16 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78633 (2013.01); H01L 27/1222 (2013.01); H01L 27/1274 (2013.01); H01L 27/1288 (2013.01); H01L 29/66757 (2013.01); H01L 29/78603 (2013.01); H01L 29/78675 (2013.01); G02F 1/1368 (2013.01); G02F 1/134363 (2013.01); G02F 2202/103 (2013.01); G02F 2202/104 (2013.01); G03F 7/16 (2013.01); G03F 7/20 (2013.01); G03F 7/30 (2013.01); H01L 27/1251 (2013.01); H01L 27/322 (2013.01); H01L 27/3262 (2013.01); H01L 27/3272 (2013.01);
Abstract
The present disclosure provides a TFT, a manufacturing method thereof, an array substrate and a manufacturing method thereof. The TFT includes a substrate, a p-Si active layer arranged on the substrate, and a first a-Si layer arranged on a surface of the p-Si active layer at a side adjacent to the substrate. An orthogonal projection of the p-Si active layer onto the substrate at least partially overlaps an orthogonal projection of the first a-Si layer onto the substrate.