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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10192965 B1

PDFFull Text
Date of Patent:
Jan. 29, 2019

Filed:

Mar. 30, 2015

Semiconductor device including first and second gate electrodes and method for manufacturing the same

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Tatsuyoshi Mihara, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McGinn IP Law Group, PLLC

Primary Examiner:

Lex Malsawma

Assistant Examiner:

Laura Dykes

Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 27/11568 (2017.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 21/02233 (2013.01); H01L 21/28282 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/3213 (2013.01); H01L 27/1157 (2013.01); H01L 27/11568 (2013.01); H01L 29/0684 (2013.01); H01L 29/4238 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01);
Abstract

A semiconductor substrate () includes a region (AR) between a region (AR) and a region (AR), a control gate electrode (CG) is formed on an upper surface (TS) of the region (AR), and a memory gate electrode (MG) is formed on an upper surface (TS) of the region (AR). The upper surface (TS) is lower than the upper surface (TS), and the region (AR) has a connection surface (TS) connecting the upper surface (TS) and the upper surface (TS). An end (EP) of the connection surface (TS) which is on the upper surface (TS) side is arranged closer to the memory gate electrode (MG) than an end (EP) of the connection surface (TS) which is on the upper surface (TS) side, and is arranged lower than the end (EP).

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