Tft array manufacturing method of optimized 4m production process

Abstract

The present invention provides a TFT array manufacturing method of an optimized 4M production process. The method includes: Step, in a first mask-based process, making a gate layer on a glass substrate and patterning the gate layer; Step, in a second mask-based process, subjecting the photoresist layer to exposure and development; conducting a first wet etching operation to pattern the source/drain layer; conducting a first oxygen ashing operation to reduce a size of trailing of the active layer on edges of the source/drain metal layer; conducing a first dry etching operation to form an active layer island structure; conducting a second oxygen ashing operation to expose portions of the source/drain layer in the channel area; conducting a second wet etching operation to pattern a source and a drain; conducting a third oxygen ashing operation to reduce trailing of the contact layer; and conducting a second dry etching operation to etch the active layer; Step, in a third mask-based process, making a passivation layer followed by patterning; and Step, in a fourth mask-based process, making a transparent electrode layer followed by patterning. The present invention allows for, on the basis of an existing production process, successful elimination of heavily doped residue in a channel area (by reducing around 0.9 um) and reducing around 1 um in an amorphous silicon area.