The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

May. 15, 2015
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zhanfeng Cao, Beijing, CN;

Feng Zhang, Beijing, CN;

Qi Yao, Beijing, CN;

Jincheng Gao, Beijing, CN;

Bin Zhang, Beijing, CN;

Xiaolong He, Beijing, CN;

Zhengliang Li, Beijing, CN;

Wei Zhang, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1345 (2013.01); G02F 1/13452 (2013.01); G02F 1/136204 (2013.01); H01L 27/12 (2013.01); G02F 1/13454 (2013.01);
Abstract

An array substrate and a display device are provided. The array substrate comprises a plurality of signal lines (), a plurality of connecting lines () and a driving module () in a peripheral region () outside a display region (); the connecting lines () are configured for connecting the signal lines () and the driving module (), to transmit signal from the signal lines () to the driving module (), wherein, at least one of the connecting lines () and at least one of the signal lines () are designed to intersect with and insulated from each other in a first region (N). The at least one of the signal lines () includes, in a second region () other than the first region (N), a first electrode line layer () and a second electrode line layer (), while, in the first region (N), includes the first electrode line layer () but does not include the second electrode line layer (). The array substrate may prevent problems of electrostatic accumulation or short circuit from occurring between the connecting lines () and the second electrode line layer ().


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