The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

May. 25, 2017
Applicant:

Fujitsu Semiconductor Limited, Yokohama, Kanagawa, JP;

Inventors:

Kazushi Fujita, Kuwana, JP;

Taiji Ema, Inabe, JP;

Mitsuaki Hori, Kuwana, JP;

Yasunobu Torii, Kuwana, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 29/167 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/26513 (2013.01); H01L 21/76224 (2013.01); H01L 21/823412 (2013.01); H01L 21/823462 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/167 (2013.01); H01L 29/6659 (2013.01); H01L 29/66477 (2013.01); H01L 29/7833 (2013.01); H01L 21/823807 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01);
Abstract

A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.


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