The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Aug. 16, 2017
Applicant:

Em Microelectronic-marin SA, Marin, CH;

Inventors:

Christoph Kuratli, Guemmenen, CH;

Yves Dupraz, Valeyres-sous-Montagny, CH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); G01R 31/317 (2006.01); G01R 31/3193 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G01R 31/31715 (2013.01); G01R 31/31937 (2013.01); H01L 23/3114 (2013.01); H01L 23/528 (2013.01); H01L 23/5286 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/48 (2013.01); H01L 23/525 (2013.01); H01L 24/49 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05015 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05551 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06167 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13028 (2013.01); H01L 2224/1613 (2013.01); H01L 2224/16106 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49175 (2013.01); H01L 2924/00014 (2013.01);
Abstract

An electronic system is provided, including an integrated circuit die having at least 2 bond pads, and a redistribution layer having at least one solder pad including 2 portions separated from each other and configured to provide an electrical connection between each of the 2 portions by a solder ball disposed on the solder pad, and to electrically isolate the 2 portions in an absence of the solder ball on the solder pad, and at least 2 redistribution wires, each connecting a different one of the portions to a different one of the bond pads, a second bond pad being connected via a second redistribution wire to a second portion being dedicated to die testing; and a grounded printed circuit board track, wherein the solder ball is disposed between the solder pad and the track, and neither of the redistribution wires traverses a separation space between the 2 portions.


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