The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Jun. 28, 2016
Applicant:

Hgst Netherlands B.v., Amsterdam, NL;

Inventors:

James Edwin O'Toole, Boise, ID (US);

Ward Parkinson, Boise, ID (US);

Daniel Robert Shepard, North Hampton, NH (US);

Thomas Michael Trent, Tucson, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0023 (2013.01); G11C 13/0004 (2013.01); H01L 27/2409 (2013.01); H01L 27/2427 (2013.01); H01L 27/2463 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01);
Abstract

The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an OTS is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above, or below the X and Y select wires, a high value resistance material, such as an OTS, may be deposited at the intersection. The OTS allows the word line or bit line to be selected without pulling excessive leakage to the select wire from the bias voltage, such as V/2. A thickness of the OTS is adjusted such that the Vof the OTS is greater than V/2, with margin, and the OTS does not turn on when the OTS is selected. A resistance is created between the V/2 wire and the word line select wire or the bit line select wire.


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