The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Jun. 14, 2016
Applicant:

Gsi Technology, Inc., Sunnyvale, CA (US);

Inventors:

Lee-Lean Shu, Los Altos, CA (US);

Paul M. Chiang, Cupertino, CA (US);

Soon-Kyu Park, San Jose, CA (US);

Gi-Won Cha, San Ramon, CA (US);

Assignee:

GSI TECHNOLOGY, INC., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 11/40 (2006.01); G06F 1/32 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G11C 11/4096 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1048 (2013.01); G06F 1/3287 (2013.01); G06F 13/4022 (2013.01); G06F 13/4077 (2013.01); G06F 13/4234 (2013.01); G11C 7/1006 (2013.01); G11C 7/1012 (2013.01); G11C 7/1072 (2013.01); G11C 11/4096 (2013.01); H01L 21/76838 (2013.01); Y02D 10/14 (2018.01); Y02D 10/151 (2018.01);
Abstract

Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.


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