The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Sep. 13, 2016
Applicant:

The United States of America As Represented BY the Director, National Security Agency, Washington, DC (US);

Inventor:

Paul Burkhardt, North Potomac, MD (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/30 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 17/30958 (2013.01); G06F 13/364 (2013.01); G06F 17/3033 (2013.01); G06F 17/30336 (2013.01); G06F 17/30377 (2013.01);
Abstract

A method includes receiving, at a master controller, a matrix representing a graph and a first vector, and initializing a counter variable and an array to track dimensionality reduction for the matrix. The method also includes multiplying a subset of the matrix based on the counter variable, by a subset of the first binary vector based on the counter variable. Multiplying includes providing, the vector and a matrix portion to a first processor, and the vector and another portion of the matrix to a second processor. The method also includes, at the processors, multiplying the vectors by the portions of the matrix and returning the results. The method also includes combining the results at the master controller. The method also includes incrementing the counter variable and updating the tracking array for larger dimensionality reduction of the matrix. The method also includes constructing the logical pathway based on the tracking array.


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