The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Dec. 30, 2016
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Kyeong Min Chae, Seoul, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G11C 8/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/068 (2013.01); G06F 3/0656 (2013.01); G11C 7/10 (2013.01); G11C 7/106 (2013.01); G11C 7/1039 (2013.01); G11C 7/1066 (2013.01); G11C 7/14 (2013.01); G11C 7/222 (2013.01); G11C 8/10 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/0483 (2013.01);
Abstract
A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.