The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Oct. 23, 2015
Applicant:

The Wuhan Digital Pet Co., Ltd, Hubei, CN;

Inventors:

Lei Fang, Hubei, CN;

Bo Zhang, Hubei, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); G06F 1/04 (2006.01); G06F 1/12 (2006.01); H04B 3/46 (2015.01); H04J 3/06 (2006.01); H04L 7/10 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0037 (2013.01); G06F 1/04 (2013.01); G06F 1/12 (2013.01); H04B 3/46 (2013.01); H04J 3/0638 (2013.01); H04L 7/0008 (2013.01); H04L 7/10 (2013.01); H04J 3/0682 (2013.01);
Abstract

A method and a device for providing a global clock in a system, the terminals in the system are channel connected to each other via paths, each terminal is communicatively connected to a clock source ultimately via a signal recording unit, respectively, the clock source sends a calibration signal to the network, the signal recording unit records the current transmitting time T () of the calibration signal, each terminal will receive the calibration signal sequentially due to different distances from the clock source and will return the signal, the backward signals are returned to the signal recording unit along the network sequentially, and the signal recording unit records the time T (n) of each backward signal sequentially, in this way, the signal recording unit can then measure the delay between each terminal and the clock source signal, which can be used as a correction parameter to ensure that all terminals are in exactly the same time reference, in addition, in this way, there is no need to control the length of the clock cables from each terminal to the clock source, and no special consideration is required for clock routing, and difficulties in system assembly, calibration, maintenance and expansion brought by large amounts of cable are avoided.


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