Metastability error correction methods and circuits for asynchronous successive approximation analog to digital converter (sar adc)

Abstract

Methods and apparatuses are described herein for metastability error detection and correction in analog-to-digital converters (ADCs). For example, an ADC may comprise a comparator, a register circuit, a first circuit, and a second circuit. The comparator may generate a comparator output signal in response to a sampling clock signal. The register circuit, operatively coupled to the comparator, may process the comparator output signal. The first circuit, operatively coupled to the comparator and the register circuit may generate a plurality of first output bits that include a bit indicating a metastability error on a condition that the metastability error occurred during the bit conversion. The second circuit, operatively coupled to the first circuit, may generate a plurality of second output bits indicating a location of the metastability error. The plurality of second output bits may be sampled using first and second groups in response to the sampling clock signal.