The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Dec. 21, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Himanshu Arora, Plano, TX (US);

Siraj Akhtar, Richardson, TX (US);

Lu Sun, Shanghai, CN;

Hamid Safiri, Plano, TX (US);

Wenjing Lu, Shanghai, CN;

Nikolaus Klemmer, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H03L 7/10 (2006.01); H03L 1/02 (2006.01);
U.S. Cl.
CPC ...
H03L 7/103 (2013.01); H03L 1/021 (2013.01); H03L 1/026 (2013.01); H03L 7/099 (2013.01); H03L 7/10 (2013.01); H03L 2207/06 (2013.01);
Abstract

A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.


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