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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10186606 B1

PDFFull Text
Date of Patent:
Jan. 22, 2019

Filed:

Jan. 13, 2016

Semiconductor device

Applicant:

Denso Corporation, Kariya, Aichi-pref., JP;

Inventor:

Masakiyo Sumitomo, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:

Posz Law Group, PLC

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 27/07 (2006.01); H01L 21/761 (2006.01); H01L 27/04 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/739 (2013.01); H01L 21/761 (2013.01); H01L 27/04 (2013.01); H01L 27/0716 (2013.01); H01L 27/0727 (2013.01); H01L 27/0761 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/0821 (2013.01); H01L 29/1095 (2013.01); H01L 29/41708 (2013.01); H01L 29/66325 (2013.01); H01L 29/7397 (2013.01); H01L 29/78 (2013.01); H01L 29/0692 (2013.01); H01L 29/0834 (2013.01);
Abstract

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.

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