The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Oct. 25, 2016
Applicant:

General Electric Company, Schenectady, NY (US);

Inventors:

Avinash Srikrishnan Kashyap, Clifton Park, NY (US);

Peter Micah Sandvik, Niskayuna, NY (US);

James Jay McMahon, Clifton Park, NY (US);

Ljubisa Dragoljub Stevanovic, Clifton Park, NY (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 29/74 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/861 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0617 (2013.01); H01L 27/0248 (2013.01); H01L 27/0251 (2013.01); H01L 27/0255 (2013.01); H01L 29/1608 (2013.01); H01L 29/7424 (2013.01); H01L 29/7811 (2013.01); H01L 29/7395 (2013.01); H01L 29/74 (2013.01); H01L 29/7802 (2013.01); H01L 29/861 (2013.01);
Abstract

A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.


Find Patent Forward Citations

Loading…