The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2019
Filed:
May. 13, 2016
Applicant:
Lam Research Corporation, Fremont, CA (US);
Inventors:
Peter Krotov, San Jose, CA (US);
Eric H. Lenz, Livermore, CA (US);
Assignee:
Lam Research Corporation, Fremont, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68735 (2013.01); H01L 21/6875 (2013.01); H01L 21/68721 (2013.01); H01L 21/68757 (2013.01); H01L 21/68785 (2013.01);
Abstract
An apparatus for semiconductor processing that includes a pedestal that includes a wafer support surface that includes a plurality of mesas and a pattern of grooves is provided. Each mesa may be bracketed between two or more grooves, each mesa may include a plurality of mesa side walls that intersect, at least in part, with one of the grooves and with a mesa top surface that is a substantially planar surface, the mesa top surfaces may be substantially coplanar with each other, and the mesa top surfaces may be configured to support a wafer during semiconductor operations.