The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Sep. 23, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co.,ltd., Hefei, CN;

Inventors:

Wei Xue, Beijing, CN;

Hongmin Li, Beijing, CN;

Zhifu Dong, Beijing, CN;

Ping Song, Beijing, CN;

Bo Liu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 5/00 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 5/003 (2013.01); G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G09G 3/3674 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01);
Abstract

The present disclosure provides a shift register, comprising: a first input module, a second input module, an energy storage module, an output module and a reset module; and two shift signal input terminals, a reset control signal input terminal, a second electrical level input terminal and a first electrical level input terminal; a control terminal and an input terminal of the first input module being connected with the first shift signal input terminal, a control terminal and an input terminal of the second input module being connected with the second shift signal input terminal; output terminals of the first input module and the second input module as well as a first terminal of the energy storage module all being connected with a first node; the first input module and the second input module being configured to be turned on when the first or second shift signal input terminal accesses a first electrical level, and set the voltage of the first node to the first electrical level. In a gate scanning circuit utilizing the shift register provided by the present disclosure, it is unnecessary to arrange VSS signal lines and VDD signal lines, which can reduce the area occupied by the corresponding gate driving circuit, and is favorable for narrowing down the frame of display panels.


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