The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Aug. 09, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Jaehoon Park, Goyang-si, KR;

Jinho Lim, Goyang-si, KR;

Cheolhwan Lee, Suwon-si, KR;

Kyunghyun Jeon, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 3/00 (2006.01); G09G 3/3266 (2016.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/006 (2013.01); G09G 3/20 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/0465 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/0213 (2013.01); G09G 2310/0221 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0283 (2013.01);
Abstract

A display device includes a display panel including a first and a second non-display area, a main active area, and a sub active area, wherein the active areas each include a matrix of sub-pixels; a data driver in the first non-display area to provide image data to the matrices of sub-pixels; a main gate driver in the second non-display area to provide a corresponding gate signal to each sub-pixel in the main active area; a sub gate driver in the second non-display area to provide a corresponding gate signal to each sub-pixel in the sub active area; an auto-probe test pad in the non-display area for transmitting a first start signal received from an auto-probe signal generating device to one of the main gate driver and the sub gate driver while testing the display panel; and a signal transmission circuit connecting the main gate driver and the sub gate driver.


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