The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Jan. 21, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventors:

Xingfeng Ren, Beijing, CN;

Chong Fang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1262 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/123 (2013.01);
Abstract

The present disclosure discloses a Thin Film Transistor array substrate, a method for manufacturing the same and a method for maintaining the same, and a display panel. The TFT array substrate includes: a substrate; gate lines, common electrode lines and data lines arranged on the substrate; and pixel electrodes arranged at pixel unit regions defined by the gate lines and the data lines. The TFT array substrate further includes weld metal electrically connected to the pixel electrodes. Projections of the weld metal onto the substrate and projections of target wires onto the substrate are overlapped at overlapping regions, and the target wires are the gate lines or the common electrode lines.


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