The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Dec. 12, 2017
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Yourui Huangfu, Hangzhou, CN;

Shaoqing Liu, Beijing, CN;

Yingchun Yang, Hangzhou, CN;

Chen Qiu, Hangzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/122 (2006.01); G02B 6/26 (2006.01); G02B 6/35 (2006.01); G02B 6/43 (2006.01); H04B 10/80 (2013.01); H04Q 11/00 (2006.01);
U.S. Cl.
CPC ...
G02B 6/122 (2013.01); G02B 6/26 (2013.01); G02B 6/3546 (2013.01); G02B 6/43 (2013.01); H04B 10/803 (2013.01); H04Q 11/0005 (2013.01);
Abstract

An on-chip optical interconnection structure and network, where the on-chip optical interconnection structure includes M levels of optical switches, and m-level optical switches in the M levels of optical switching devices include 2optical switches. Each optical switch in (i-1)-level optical switches in the M levels of optical switches is coupled to two optical switches in i-level optical switches. Two optical switches in the i-level optical switches coupled to a same optical switch in the (i-1)-level optical switches are coupled. The on-chip optical interconnection network is divided into levels, and switches coupled in a grid manner are formed such that hierarchical switching may be performed, and conflicts and delays in communication are reduced.


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