The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Apr. 27, 2018
Applicant:

Verily Life Sciences Llc, South San Francisco, CA (US);

Inventors:

Mandy Philippine, San Carlos, CA (US);

Scott Matula, Alameda, CA (US);

Johan Vanderhaegen, Cupertino, CA (US);

Louis Jung, Foster City, CA (US);

Nivi Arumugam, San Francisco, CA (US);

Assignee:

VERILY LIFE SCIENCES LLC, South San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); A61B 5/145 (2006.01); A61B 5/00 (2006.01); A61B 5/157 (2006.01); A61B 5/1486 (2006.01);
U.S. Cl.
CPC ...
A61B 5/14532 (2013.01); A61B 5/1486 (2013.01); A61B 5/157 (2013.01); A61B 5/6801 (2013.01);
Abstract

An example continuous glucose monitor includes a printed circuit board ('PCB') having first and second outer layers and an inner layer, the inner layer disposed between the first and second outer layers; a semiconductor package having four corner portions and a plurality of pins, the semiconductor package coupled to the first outer layer of the PCB via the plurality of pins; an electrical ground plane formed on the PCB and coupled to at least one pin at each of a first, second, and third of the four corner portions, and not coupled to any pins at a fourth corner portion; an electrical contact for a sensor wire formed on the second outer layer of the PCB; a sensor trace having a first portion disposed on the first outer layer, a second portion disposed on the inner layer, and a third portion disposed on the second outer layer, the sensor trace having a first end coupled to a first pin of the plurality of pins and a second end coupled to the electrical contact for the sensor wire, the first pin at the fourth corner of the semiconductor package; a plurality of guard rings disposed on the PCB, each guard ring encircling one of the portions of the sensor trace; and an encapsulant disposed around a perimeter of the semiconductor package, the encapsulant covering (i) the plurality of pins, (ii) the first portion of the sensor trace, (iii) the third portion of the sensor trace, wherein an upper surface of the semiconductor package remains exposed.


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