The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Nov. 04, 2013
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Petrus Sundgren, Regensburg, DE;

Markus Broell, Freising, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 21/00 (2006.01); H01L 33/14 (2010.01); H01L 33/40 (2010.01); H01L 31/0232 (2014.01); H01L 31/0304 (2006.01); H01L 31/18 (2006.01); H01L 33/30 (2010.01); H01L 33/38 (2010.01); H01L 33/32 (2010.01);
U.S. Cl.
CPC ...
H01L 33/14 (2013.01); H01L 31/02327 (2013.01); H01L 31/03042 (2013.01); H01L 31/186 (2013.01); H01L 31/1852 (2013.01); H01L 33/0066 (2013.01); H01L 33/0095 (2013.01); H01L 33/305 (2013.01); H01L 33/40 (2013.01); H01L 33/405 (2013.01); H01L 33/0079 (2013.01); H01L 33/32 (2013.01); H01L 33/387 (2013.01); H01L 2933/0016 (2013.01);
Abstract

An optoelectronic semiconductor chip () is provided which has a semiconductor body comprising a semiconductor layer sequence () with an active region () provided for generating and/or receiving radiation, a first semiconductor region () of a first conduction type, a second semiconductor region () of a second conduction type and a cover layer (). The active region () is arranged between the first semiconductor region () and the second semiconductor region () and comprises a contact layer () on the side remote from the active region. The cover layer () is arranged on the side of the first semiconductor region () remote from the active region () and comprises at least one cut-out (), in which the contact layer () adjoins the first connection layer (). The cover layer is of the second conduction type. Furthermore, a method is provided for producing optoelectronic semiconductor chips.


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