The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Oct. 05, 2016
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Dahye Shim, Gyeonggi-do, KR;

Haye Kim, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/2092 (2013.01); G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A shift register and a display device including the same are provided. The shift register includes a first stage sequentially outputting a gate pulse to first and second gate lines of a pixel array corresponding to a voltage of a first Q node and a second stage sequentially outputting the gate pulse to third and fourth gate lines of the pixel array corresponding to a voltage of a second Q node. The first stage includes a start controller charged with the voltage of the first Q node, a first pull-up transistor increasing a voltage of a first output terminal in response to the voltage of the first Q node and a first gate clock, and a second pull-up transistor increasing a voltage of a second output terminal in response to the voltage of the first Q node and a second gate clock.


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