The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Dec. 20, 2017
Applicant:

Liqid Inc., Lafayette, CO (US);

Inventors:

Jason Breakstone, Broomfield, CO (US);

German Kazakov, Longmont, CO (US);

Christopher R. Long, Colorado Springs, CO (US);

James Scott Cannata, Denver, CO (US);

Assignee:

Liqid Inc., Broomfield, CO (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 12/02 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 9/5044 (2013.01); G06F 9/5077 (2013.01); G06F 12/02 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01); G06T 1/20 (2013.01);
Abstract

Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a data processing system is provided. The method includes communicatively coupling graphics processing units (GPUs) over a Peripheral Component Interconnect Express (PCIe) fabric. The method also includes establishing a peer-to-peer arrangement between the GPUs over the PCIe fabric by at least providing an isolation function in the PCIe fabric configured to isolate a device PCIe address domain associated with the GPUs from at least a local PCIe address domain associated with a host processor that initiates the peer-to-peer arrangement between the GPUs.


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