The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2019
Filed:
Aug. 19, 2016
Applicant:
Electronics and Telecommunications Research Institute, Daejeon, KR;
Inventors:
Jin Ho Han, Seoul, KR;
Young-Su Kwon, Daejeon, KR;
Kyung Jin Byun, Daejeon, KR;
Nak Woong Eum, Daejeon, KR;
Assignee:
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/0842 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/084 (2013.01); G06F 12/0842 (2013.01); G06F 12/0875 (2013.01); G06F 2212/6042 (2013.01); G06F 2212/62 (2013.01);
Abstract
Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.