The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Jun. 05, 2017
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Alexander Bazarsky, Holon, IL;

Eran Sharon, Rishon Lezion, IL;

Yuri Ryabinin, Beer-Sheva, IL;

Yan Dumchin, Beer-Sheva, IL;

Idan Alrod, Herzeliya, IL;

Ariel Navon, Revava, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 29/52 (2006.01); H03M 13/11 (2006.01); H03M 13/37 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1012 (2013.01); G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); H03M 13/1102 (2013.01); H03M 13/1108 (2013.01); H03M 13/1111 (2013.01); H03M 13/3707 (2013.01); H03M 13/3723 (2013.01); H03M 13/612 (2013.01); H03M 13/6325 (2013.01);
Abstract

A data storage device may include a memory and a controller that includes an error correction coding (ECC) decoder configured to operate in a plurality of decoding modes. The controller also includes a bit error rate estimator configured to determine, based on data received from the memory, bit error rate estimates for ECC codewords from the memory. The controller also includes a data path management unit configured to reorder the codewords based on the bit error rate estimates and to provide the reordered codewords to the ECC decoder.


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